1. Field of the Invention
The invention relates generally to integrated circuits. More particularly, the invention relates to buried via technology for three dimensional integrated circuits.
2. Description of Related Art
Three dimensional integrated circuit (IC) technology provides powerful capability for increased IC functionality. The three dimensional IC technology utilizes a multi-layer of active circuitry stacked up one on top of the other. Each active layer may consist of several metal layers with a thickness of about 1 micron each, forming an electric interconnect network between active devices, such as transistors.
To fully exploit three dimensional IC technology, high density vertical interconnects with conductive wiring between stacked active circuit layers is required. FIG. 1 illustrates a prior art vertical interconnect, such as a through via 11, between metal layers 13, 15, 17 and 19 for active circuitry. The size of through via 11 should be compatible with feature size of the underlying lateral process technology.
Most approaches to three-dimensional IC technology rely on through via 11. However, through vias 11 have several disadvantages. First, through vias 11 create an exclusion zone that interrupts the routing in all metal layers 13, 15, 17 and 19, as shown in FIG. 1. Through vias 11 penetrate, not only through a wafer 21, but also through the stacked metal layers 13, 15, 17 and 19 and interrupt the circuit routing.
This creates exclusion area constraints that make combination with state of the art 2-dimensional circuit technologies difficult and inefficient.
Second, routing streets in line with through via 11 are blocked by the through via 11, as shown in FIG. 2. A conductive wiring 23 coated with an interlayer dielectric travels through the via 11. This wiring 23 blocks the routing of streets 25 and 27 in line with the through via 11. Hence, the routing streets are blocked in both dimensions, on all metal layers.
Third, the top level metal routing street in line with the landing pad 33, for example metal layer 19, is blocked by the landing pad 33, as shown in FIG. 2. The conductive wiring 23 travels through the via 11, comes out of via 11, and goes through at least the top metal layer 19 at the location of the landing pad 33.
Consequently, the landing pad 33 blocks the routing in streets 29 and 31 in line with the landing pad 33. Hence, the routing streets are blocked on the top metal layer 19 at the landing pad 33 as well. Since the top metal layer 19 typically has the lowest electrical resistance of all metal layers in an integrated circuit process, it is used for power routing. Blocking this power routing layer is problematic.
With an ever increasing demand for improved integrated circuits technology, there remains a need in the art for buried via technology in three dimensional integrated circuits that provides a high density vertical interconnect with minimal exclusion zones while maintaining compatibility with two dimensional processed integrated circuits.